K. Raleva1, X. Zhang2, S. S. Qazi2, T. Thornton2 and D. Vasileska2

1FEIT, UKiM, Skopje, Republic of Macedonia

2School of ECEE, Arizona State University, Tempe, AZ, USA

The continuous miniaturization trend in microelectronic design has pushed the transistor gate length to a range of tens of nanometers. The downscaling of MOSFET devices is not without problems, however. It has necessitated the use of high-k dielectrics, strain and alternative device designs such as fully-depleted SOI devices, dual-gate structures, FinFETs, etc. Increasing power dissipation and decreasing device dimensions also exacerbates device self-heating effects, causing an overall degradation of the on-current due to the characteristic phonon hot-spot near the drain end of the channel, which does not scale proportionally.

Self-heating effect is particularly important for transistors in Silicon-On-Insulator (SOI) technology where the device is separated from the substrate by a low thermal conductivity buried silicon dioxide layer, as well as copper interconnects that are surrounded by low thermal conductivity dielectric materials. This, in turn, leads to a substantial elevation of the local device temperature which modifies the device output characteristics. Another important aspect that needs to be considered in nanoscale SOI devices, is a reduction of the thermal conductivity in semiconductor thin films. For instance, bulk silicon (Si) has a thermal conductivity of 148 W/m/K, while 10 nm Si-film has around 10 times smaller thermal conductivity value. This reduction of thermal conductivity in semiconductor thin film with thickness less than the phonon mean free path is due to the increased importance of phonon boundary scattering.

Since lattice temperature, being an internal variable, is almost impossible to be measured, a combination of experiment with accurate modeling technique is a must in determining the temperature of the hot-spot. In this talk we present a novel multi-scale simulation approach that combines circuit level with device level simulations together with experimental measurements to uncover the temperature of the hot-spot in nanoscale SOI MOSFET.

The theoretical model used in this research work is based on a measurement technique developed by IMEC, in which a T (hot-spot temperature increase) is extracted using temperature dependent characteristics of a neighboring MOSFET in common source (CS) or common drain (CD) configuration. Simulations were performed using the device simulator developed at ASU that can co-simulate multiple devices. The group at ASU has extended the formalism of Lai and Majumder and self-consistently coupled the 2D particle-based device simulator to the 2D energy balance equations solvers for the optical and the acoustic phonon baths. The exchange of variables between the two solvers is such that the drift velocity, electron density and electron temperature are input parameters to the energy balance solver. The local acoustic and optical phonon temperatures are obtained from energy balance equations solver and this information is used in conjunction with the temperature dependent scattering tables. The device simulator gives rise to more pronounced hot-spot because it accurately represents the optical to acoustic phonon bottleneck, which is not the case for commercial device simulators where Joule heating model is used.